Use of a differential configuration, as in emitter-coupled logic (ECL), typically enables an electronic circuit to switch very fast. Referring to the drawings, FIG. 1 illustrates a conventional ECL gate that switches between a pair of binary logic states. The gate operates in response to a differential input voltage signal V.sub.I formed by the difference V.sub.I1 -V.sub.I2 between a pair of input voltages V.sub.I1 and V.sub.I2, one of which may be a substantially fixed reference voltage. Responsive to differential input V.sub.I, the gate produces a pair of complementary output voltage signals V.sub.O1 and V.sub.O2 whose relative values characterize the gate's condition. The gate consists of a differential input stage 10 and an output stage 12.
Input stage 10 centers around a pair of largely identical differentially configured NPN input transistors QI1 and QI2whose bases receive input voltages V.sub.I1 and V.sub.I2. A substantially constant current source 14 connected to a source of a low supply voltage V.sub.EE provides a supply current I.sub.E to the interconnected emitters of transistors QI1 and QI2. Their collectors are coupled through equal-value resistors RC1 and RC2 to a source of a high supply voltage V.sub.cc. Complementary intermediate voltage signals V.sub.M1 and V.sub.M2 are supplied from the QI1 and QI2collectors as outputs of stage 10.
Turning to output stage 12, it contains largely identical NPN output transistors QO1 and QO2 whose bases receive intermediate voltages V.sub.M1 and V.sub.M2. The collectors of transistors QO1 and QO2 are tied to the V.sub.cc supply. Their emitters carry currents I.sub.A1 and I.sub.A2. The QO1 and QO2 emitters are connected to nodes N1 and N2 from which output voltages V.sub.O1 and V.sub.O2 are taken. Output currents I.sub.01 and I.sub.02 flow out of the V.sub.O1 and V.sub.O2 output terminals. Largely identical substantially constant current sources 16 and 18, which are connected to the V.sub.EE supply, provide supply currents I.sub.S1 and I.sub.S2 at nodes N1 and N2.
The gate in FIG. 1 drives a parasitic load capacitance represented by capacitors CL1 and CL2. Capacitor CL1 is connected between node N1 and the V.sub.EE supply. Capacitor CL2 is similarly connected between node N2 and the V.sub.EE supply. Capacitive load currents I.sub.L1 and I.sub.L2 flow into (the upper plates of) capacitors CL1 and CL2.
The gate switches from one binary state to the other as differential input V.sub.I goes from a voltage less than -60 millivolts to a voltage greater than 60 millivolts, and vice versa. A better understanding of the switching operation is facilitated with the assistance of the waveforms shown in FIG. 2. Supply currents I.sub.S1 and I.sub.S2 have largely the same value during normal operation (since current sources 16 and 18 are largely identical). This value is represented by the symbol "I.sub.s " in FIG. 2.
Assume V.sub.I is initially somewhat less than -60 millivolts as denoted by the "-" sign in FIG. 2. Transistor QI1 is non-conductive. V.sub.M1 (not shown in FIG. 2) is at a high voltage V.sub.MH very close to V.sub.cc. Transistor QI2 is fully turned on and draws current I.sub.E through resistor RC2. V.sub.M2 (also not shown in FIG. 2) is at a low voltage V.sub.ML.
Transistors QO1 and QO2 are both turned on. V.sub.O1 is at a high voltage V.sub.OH that is approximately 1V.sub.BE below V.sub.MH. V.sub.BE is the magnitude of the standard voltage (approximately 0.8 volt) across the base-emitter junction of a bipolar transistor when it is fully conductive. Similarly, V.sub.O2 is at a low voltage V.sub.OL approximately 1V.sub.BE below V.sub.ML. I.sub.L1 and I.sub.L2 are both zero. Capacitor CL1 is charged to a high level, while capacitor CL2 is charged to a low level.
When V.sub.I is raised to a value somewhat greater than 60 millivolts as denoted by the "+" sign in FIG. 2, transistor QI2 turns off. Transistor QI1 turns on and draws current I.sub.E through resistor RC1. V.sub.M1 is thus pulled down to V.sub.ML, causing transistor QO1 to become temporarily less conductive. V.sub.O1 drops down to V.sub.OL during a fall time t.sub.F, after which transistor QO1 returns to its initial conductive level.
The mechanism by which V.sub.O1 is reduced to V.sub.OL involves discharging capacitor CL1 to a suitably low level. Capacitor CL1 discharges primarily through current source 16. Very little of the CL1 discharge occurs through the V.sub.O1 output terminal, I.sub.O1 typically consisting of the small current flowing into the base of an input transistor in a gate driven by the gate shown in FIG. 1. Consequently, the value that I.sub.L1 can reach during the switching transition is largely limited by the value of I.sub.S1. In particular, the maximum magnitude of I.sub.L1 is largely equal to I.sub.S during the transition, as indicated in the left half of FIG. 2.
As V.sub.M1 drops down to V.sub.ML, V.sub.M2 is pulled up to V.sub.MH. Transistor QO2 pulls V.sub.O2 up to V.sub.OH during a rise time t.sub.R. More specifically, transistor QO2 temporarily becomes more conductive during time t.sub.R. The resulting increase in I.sub.A2 enables I.sub.L2 to increase temporarily in the manner depicted in the left half of FIG. 2. Capacitor CL2 is thereby charged to a high level.
The amount that I.sub.A2 can increase during the switching transition is normally considerably greater than I.sub.S. I.sub.L2 thus reaches a value substantially greater than I.sub.S and, accordingly, much greater than I.sub.L1. Higher charge/discharge current means shorter rise/fall time. As a result, t.sub.R is significantly less than t.sub.F.
The reverse events occur when V.sub.I is returned to a value less than -60 millivolts. See the right half of FIG. 2 where t.sub.R now represents the rise time for V.sub.O1, and t.sub.F represents the fall time for V.sub.O2. Again, t.sub.R is significantly less than t.sub.F. For the reasons given above, the minimum value of t.sub.F is limited by the value of I.sub.S. The switching speed of the gate in FIG. 1 is thus limited by supply current I.sub.S.
Making current sources 16 and 18 larger--i.e., increasing I.sub.S --is disadvantageous because the steady-state current requirements of the gate increase proportionately. A commensurate increase in power dissipation occurs. It is desirable to increase the switching speed of an ECL gate of the type shown in FIG. 1 without drawing any significant additional steady-state current.